Реклама:

1. Adams, М., and Dulchinos, D. "OpenCable", IEEE Commun. Magazine, vol. 39, pp. 98-105, June 2001.

2. Adiga, NR. et al. "An Overview of the BlueGene/L Supercomputer", Proc. Supercomputing 2002, ACM, pp. 1-22, 2002.

3. Adve, S. V., and Charachorloo, K. "Shared Memory Consistency Models: A Tutorial", IEEE Computer Magazine, vol. 29, pp. 66-76, Dec. 1996.

4. Adve, S. V., and Hill, M. "Weak Ordering: A New Definition", Proc. 17th Ann. Infi. Symp. on Computer Arch, ACM, pp. 2-14, 1990.

5. Agerwala, Т., and Cocke,J. "High Performance Reduced Instruction Set Pro-cessors", IBM T.J. Watson Research Center Technical Report RC12434, 1987.

6. Alameldeen, A.R., and Wood, DA. "Adaptive Cache Compression for High-Performance Processors". Proc. 31st Ann. Int'l Sym. on Computer Arch. ACM, pp. 212-223, 2004.

7. Almasi, G. S. et al. "System Management in the BlueGene/L Supercomputer", Proc. 17th Int'l Parallel and Distr. Proc. Symp., IEEE, 2003a.

8. Almasi, G.S. et al. "An Overview Of The Bluegene/L System Software Organization", Par. Proc. Letters, vol. 13, 561-574, April 2003b.

9. Amza, C, Cox, A., Dwarkadas, S., Keleher, P., Lu, H, Rajamony, R., Yu, W., Zwae-nepoel, W. "TreadMarks: Shared Memory Computing on a Network of Workstations", IEEE Computer Magaxine, vol. 29, pp. 18-28, Feb. 1996.

10. Anderson, D. Universal Serial Bus System Architecture, Reading, MA: Addison-Wesley, 1997.

11. Anderson, D., Budruk, R., and Shanley, T. PCI Express System Architecture, Reading, MA: Addison-Wesley, 2004.

12. Anderson, Т. E., Cutter, D. E., Patterson, D. A., and the NOW team "A Case for NOW (Networks of Workstations)", IEEE Micro Magazine, vol. 15, pp. 54-64, Feb. 1995.

13. Antonakos,J. L. The Pentium Microprocessor, Upper Saddle River, NJ: Prentice Hall, 1997.

14. August, D. L, Connors, D. A., Mshlke, S. A., SIAS, J. W., Crozier, К. M., Cheng, B.-C, Eaton, P. R., Olaniran, Q В., and HWU, W.-M. "Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture, Proc. 25th Ann. Int'l. Symp. on Computer Arch, ACM, pp. 227-237, 1998.

15. Ayala, K. The 8051 Microcontoller, 3rd ed, Clifton Park, NY: Thomson Delmar Leaning, 2004.

16. Bai, H. E. Programming Distributed Sysyterns, Hemel Hempstead, England: Prentice Hall Int'l, 1991.

17. Bai, H. E., Bhoedjang, R., Hofman, R, Jacobs, C, Langendoen, K., Ruhl, Т., and Kaashoek, M. F. "Performance Evaluation of the Orca Shared Object System", ACM Trans, on Computer Systems, vol. 16, pp. 1-40, Feb. 1998.

18. Bal, H. E., Kaashoek, M.F., and Tanenbaum, A. S. "Orca: A Language for Parallel Programming of Distributed Systems", IEEE trans, on Software Engeneering, vol. 18, pp. 190-205, March 1992.

19. Bal, H. E., and Tanenbaum, A. S. "Distributed Programming with Shared Data", Proc. 1988 Intl. Conf. on Computer Languages, IEEE, pp. 82-91, 1988.

20. Barroso, L.A., Dean J., Holzle, U. "Web Search for a Planet: The Google Cluster Architecture*, IEEE Micro Magazine, vol. 23, pp. 22-28, March-April 2003.

21. Bechini, A., Conte, T.M., and Prete, C.A. "Opportunities and Challenges in Embedded Systems", IEEE Micro Magazine, vol. 24, pp. 8-9, July-Aug. 2004.

22. Benini, L., and De Micheli, G. "Networks on Chips. A New SoC Paradigm", IEEE Computer Magazine, vol. 35, pp. 70-78, Jan. 2002.

23. Berman, F., Fox, G., and Hey, AJ.G. "Grid Computing: Making the Global Infrastructure a Reality", Hoboken, NJ: John Wiley, 2003.

24. Bjornson, R. D. "Linda on Distributed Memory Multiprocessors*, Ph. D. Thesis, Yale Univ., 1993.

25. Blum, R. Professional Assembly Language, New York: Wiley, 2005.

26. Blumrich, M., Chen, D., Chiu, G., Coteus, P., Gara, A., Giampapa, M.E., Having, RA., Heidelberger, P., Hoenicke, D., Kopcsay, G.V., Ohmacht, M., Steinmacher-Burow, B.D., Takken, T, Vransas, P., and Liebsch, T. "An Overview of the BlueGene/L System", IBM J. Research and Devel., vol. 49, March-May, 2005.

27. Borkar, S. "Getting Gigascale Chips", Queue, pp. 26-33, Oct. 2003.

28. Bose, P. "Computer architecture research: Shifting priorities and newer challenges", IEEE Micro Magazine, vol. 24, p. 5, Nov-Dec. 2004.

29. Bouknight, W.J., Denenberg, S. A., Mcintyre, D. E., Randall,]. M., Sameh, A. H, and Slotnick, D. L. "The Illiac IV System", Proc. IEEE, pp. 369-388, April 1972.

30. Brightwell, R., Camp, W., Cole, B., DeBenedictis, Leland, R, and Tompkins, J. "Archi-tectural Specification for Massively Parallel Computers - An Experience and Measurement-Based Approach", ftp://ftp.cs.sandia.gov/pub/papers/bright/ redstorm-ccpe04.pdf.

31. Bryant, R.E., and O'Hallaron, D. Computer Systems: A Programmer's Perspective Upper Saddle River, NJ: Prentice Hall, 2003.

32. Buchanan, W., Wilson, A. Advanced PC Architecture, Reading, MA: Addison-Wesley, 2001.

33. Burger, D., and Goodman, J.R. "Billion-Transistor Architectures: There and Back Again", IEEE Computer Magazine, vol. 37, pp. 22-28, March 2004.

34. Burkhardt, H., Frank, S., Knobe, B., and Rothnie,]. "Overview of the KSR-1 Computer System", Technical Report KSR-TR-9202001, Kendall Square Research Corp, Cambridge, MA, 1992.

35. Cain, H., and Lipasti, M. "Memory Ordering: A Value-Based Approach", Proc. 31th Ann. Int'l Symp. on Computer Arch., ACM, pp. 90-101, 2004.

36. Calcutt, D., Cowan, F., and Parchizadeh, H. 8051 Microcontrollers: An Applications Based Introduction, Oxford: Newnes, 2004.

37. Carriero, N., and Gelernter, D. "Linda and Context", Commun, of the ACM, vol. 32, pp. 444-458, April 1989.

38. Charlesworth, A. "The Sun Fireplane Interconnect ", IEEE Micro Magazine, vol. 22, pp. 36-45, Jan.-Feb. 2002.

39. Charlesworth, A. "The Sun Fireplane Interconnect ", Proc. Conf. on High Perf. Networking and Computing, ACM, 2001.

40. Charlesworth, A., Phelps, A., Williams, R., and Gilbert, G. "Gigaplane-XB: Extending the Ultra Enterprise Family", Proc. Hot Interconnects V, IEEE, 1998.

41. Chen, L., Dropsho, S., Albonesi, D.H. "Dynamic Data Dependence Tracking and its Application to Branch Prédiction", Proc. Ninth Int'l Symp. on High-Performance Computer Arch, IEEE, pp. 65-78, 2003.

42. Chou, 7, Fahs, B., Abraham, S. "Microarchitecture Optimizations for Exploiting Memory-Level Parallelism", CQ Proc. 31st Ann. Int'l Symp. on Computer Arch, ACM, pp. 76-77, 2004.

43. Claasen, T.A.C.M. "System on a Chip: Changing IC Design Today and in the Future", IEEE Micro Magazine, vol. 23, pp. 20-26, May-June 2003.

44. Cody, W.J. "Analysis of Proposals for the Floating-Point Standard", IEEE Computer Magazine, vol. 14, pp. 63-68, Mar. 1981.

45. Cohen, D. "On Holy Wars and a Plea for Peace", IEEE Computer Magazine, vol. 14, pp. 48-54, Oct. 1981.

46. Colwell, R. The Pentium Chronicles New York: Wiley, 2005.

47. Comer, D.E. "Network Systems Design Using Network Processors: Agere Version", Upper Saddle River, NJ: Prentice Hall, 2005.

48. Corbato, F.J. "PL/1 as a Tool for System Programming", Datamation, vol. 15, pp. 68-76, May 1969.

49. Corbato, F. J., and Vyssotsky, V. A. "Introduction and Overview of the MULTICS System", Proc. FJCC, pp. 185-196, 1965.

50. Crowley, P., Franklin, MA., Hadimioglu, H., and Onufryk, P.Z. Network Processor Design: Issues and Practices, Vol. 1, San Francisco: Morgan Kaufmann, 2002.

51. Dally, W.J., and Towles, B.P. Principles and Practices of Interconnection Networks, San Francisco: Morgan Kaufmann, 2004.

52. Daneshbeh, A.K., and Hasan, M.A. "Area Efficient High Speed Elliptic Curve Cryptoprocessor for Random Curves", Proc. Int'l Conf. on Inf. Tech.: Coding Speculative Execution and Computing, IEEE, pp. 588-593, 2004.

53. Dean, A.G. "Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers", IEEE Micro Magazine, vol. 24, pp. 10-22, July-Aug. 2004.

54. Denning, P.J. "The Working Set Model for Program Behavior", Commun, of the ACM, vol. 11, pp. 323-333, May 1968.

55. Dijkstra, E. W. "GOTO Statement Considered Harmful", Commun, of the ACM, vol. 11, pp. 147-148, Mar. 1968a.

56. Dijkstra, E. W. "Co-operating Sequential Processes", in Programming Languages, F. Genuys (ed.), New York: Academic Press, 1968b.

57. Donaldson, G, and Jones, D. "Cable Television Broadband Network Architectures", IEEE Commun. Magazine, vol. 39, pp. 122-126, June 2001.

58. Dongarra,J., Foster, 7, Fox, G, Gropp, W., Kennedy, K, Torczon, I, and White, A. The Sourcebook of Parallel Computing. San Francisco: Morgan Kaufman, 2003.

59. Dubois, M., Scheurich, C, and Briggs, F A. "Memory Access Buffering in Multiprocessor, Proc. 13th Ann. Int'l. Symp. on Computer Arch, ACM, pp. 434-442, 1986.

60. Dulong, C. "The IA-64 Architecture at Work", IEEE Computer Magazine, vol. 31, pp. 24-32, July 1998.

61. Dutta-Roy, A. "An Overview of Cable Modem Technology and Market Perspectives", IEEE Commun. Magazine, vol. 39, pp. 81-88, June 2001.

62. Eschmann, F., Klauer, B., Moore, R., and Waldschmidt, K. "SDAARC: An Extended Cache-Only Memory Architecture", IEEE Micro Magazine, vol. 22, pp. 62-70, May-June, 2002.

63. Faggin} F.} Hoff, M. E.,Jr.} Mazor, S., and Shima, M. "The History of the 4004", IEEE Micro Magazine, vol. 16, pp. 10-20, Nov. 1996.

64. Falcon, A., Stark, J., Ramirez, A., Lai, K, and Valero, M. " Prophet/Critic Hybrid Branch Prédiction", Proc. 31th Ann. Int'l Symp. on Computer Arch, ACM, pp. 250-261, 2004.

65. Fisher, J. A., and Freudenberger, S. M. "Predicting Conditional Branch Directions from Previous Runs of a Program", Proc. 5th Conf. on Arch. Support for Prog. Lang, and Operating Syst, ACM, pp. 85-95, 1992.

66. Floyd, T. L. Digital Fundamentals, 6th ed. Upper Saddle River, NJ: Prentice Hall, 1997.

67. Flynn, D. "AMBA: Enabling Reusable On-Chip Designs", IEEE Micro Magazine, vol. 17, pp. 20-27, July 1997.

68. Flynn, M.J. "Some Computer Organizations and Their Effectiveness", IEEE Trans, on Computers, vol. C-21, pp. 948-960, Sept. 1972.

69. Foster, L, and Kesselman, C. The Grid 2: Blueprint for a New Computing Infrastructure, San Francisco: Morgan Kaufman, 2003.

70. Foster, 7, Kesselman, C., Nick, J.M, and Tuecke, S. "Grid Services for Distributed Systems Intégration", IEEE Computer Magazine, vol. 35, pp. 37-46, June 2002.

71. Foster, 7, and Kesselman, C. "Globus: A Metacomputing Infrastructure Toolkit", Int'l. J. of Supercomputer Applications, vol. 11, pp. 115-128, 1998a.

72. Foster, 7, and Kesselman, C. "The Globus Project: A Status Report", IPPS/ SPDP '98 Heterogeneous Computing Workshop, IEEE, pp. 4-18, 1998b.

73. Fotheringham,]. "Dynamic Storage Allocation in the Atlas Computer Including an Automatic Use of a Backing Store", Commun. of the ACM, vol. 4, pp. 435-436, Oct. 1961.

74. Geist, A., Beguelin, A., Dongarra, JJiang, W., Mancheck, R., and Sunderram, V. PVM: Parallel Virtual Machine - A User's Guide and Tutorial for Networked Parallel Computing, Cambridge, MA: M.I.T. Press, 1994.

75. Gerber, R., and Binstock, A. Programming with Hyper-Threading Technology, Santa Clara, CA: Intel Press, 2004.

76. Ghemawat, S., Gobioff H., and Leung, S.-T. "The Google File System," Proc. 19th Symp. on Operating Systems Principles, ACM, pp. 29-43, 2003.

77. Goodman,]. R. "Using Cache Memory to Reduce Processor Memory Traffic", Proc. 10th Ann. Int'l. Symp. on Computer Arch., ACM, pp. 124-131, 1983.

78. Goodman J. R. "Cache Consistency and Sequential Consistency*, Tech. Rep. 61, IEEE Scalable Coherent Interface Working Group, IEEE, 1989.

79. Grimshaw, A. S., and Wulf, W. "Legion: A View from 50,000 Feet", Proc. Fifth Int'l. Symp. on High-Performance Distributed Computing, IEEE, pp. 89-99, Aug. 1996.

80. Grimshaw, A. S., and Wulf, W. "The Legion Vision of a Worldwide Virtual Com-puter", Commun. of the ACM, vol. 40, pp. 39-45, Jan. 1997.

81. Gropp, W., Lusk, E., and Skjellum, A. "Using MPI: Portable Parallel Programming with the Message Passing Interfaces*, Cambridge, MA: M.I.T. Press, 1994.

82. Gurumurthi, S., Sivasubramaniam, Kandemir, M., and Franke, H. "Reducing Disk Power Consumption in Servers with DRPM", IEEE Computer Magazine, vol. 36, pp. 59-66, Dec. 2003.

83. Hagersten, E., Landin, A., Haridi, S. "DDM - A Cache-Only Memory Architec-ture", IEEE Computer Magazine, vol. 25, pp. 44-54, Sept. 1992.

84. Hamacher, V. V., Vranesic, Z G., and Zaky, S. G. Computer Organization, 5th ed., New York: McGraw-Hill, 2001.

85. Hamming, R. W. "Error Detecting and Error Correcting Codes", Bell Syst. Tech. J., vol. 29, pp. 147-160, April 1950.

86. Hammond, L., Wong, V., Chen, M., Hertzberg, B, Davis, J., Carlstrom, B., Prabhu, M., Wijaya, H, Kozyrakis, C, and Olukotun, K. transactional Memory Coherence and Consistency*, Proc. 31th Ann. Int'l Symp. on Computer Arch., ACM, pp. 102-113, 2004.

87. Handy, J. The Cache Memory Book, 2nd ed., Orlando, FL: Academic Press, 1998.

88. Hart,J. M. Win32 System Programming, Reading, MA: Addison-Wesley, 1997.

89. Heath, S. Embedded Systems Design, Oxford: Newnes, 2003.

90. Henkel,J., Hu, X.S., and Bhattachaiyya, S.S. "Taking on the Embedded System Challenge*, IEEE Computer Magazine, vol. 36, pp. 35-37, April 2003.

91. Hennessy, J. L. "VLSI Processor Architecture*, IEEE Trans, on Computers, vol. C-33, pp. 1221-1246, Dec. 1984.

92. Hennessy, J.L., and Patterson, D.A. Computer Architecture A Quantitative Approach, 3rd ed. San Francisco: Morgan Kaufmann, 2003.

93. Hill, M. "Multiprocessors Should Support Simple Memory-Consistency Models", IEEE Computer Magazine, vol. 31, pp. 28-34, Aug. 1998.

94. Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P. "The Microarchtecture of the Pentium 4", Intel Technology Journal, vol. 5, pp. 1-12, Jan-March, 2004.

95. Hoare, C. A. R. "Monitors, An Operating System Structuring Concept", Commun. of the ACM, vol. 17, pp. 549-557, Oct. 1974; Erratum in Commun. of the ACM, vol. 18, p. 95, Feb.1975.

96. Huh, J., Burger, D., Chang, J., and Sohi, G.S. "Speculative Incoherent Cache Pro-tocols", IEEE Micro Magazine, vol. 24, pp. 104-109, Nov.-Dec. 2004.

97. Hwang, K, and Xu, Z. Scalable Parallel Computing, New York: McGraw-Hill, 1998.

98. Hwu, W.-M. introduction to Predicated Executions IEEE Computer Magazine, vol. 31, pp. 49-50, Jan. 1998.

99. Irvine, K. Assembly Language for Intel-Based Computers, 4th ed. Upper Saddle River, NJ: Prentice Hall, 2002.

100. Jacob, B., and Mudge, T. "Virtual Memory: Issues of Implementation, IEEE Computer Magazine, vol. 31, pp. 33-43, June 1998a.

101. Jacob, B., and Mudge, T. "Virtual Memory in Contemporary Microprocessor, IEEE Micro Magazine, vol. 18, pp. 60-75, July/Aug. 1998b.

102. Jerraya, A. A., and Wolf. W. Multiprocessor Systems-on-a-Chip, San Francisco: Morgan Kaufmann, 2005.

103. Jimenez, D.A. "Fast Path-Based Neural Branch Predictions Proc. 36th Int'l Symp. on Microarchitecture, IEEE, pp. 243-252, 2003.

104. Johnson, K. I, Kaashoek, M. F., and Wallach, D. A. "CRL: High-Performance All-Software Distributed Shared Memory", Proc. 15th Symp. on Operating Systems Principles, ACM, pp. 213-228, 1995.

105. Johnson, M. Superscalar Microprocessor Design, Englewood Cliffs, NJ: Prentice Hall, 1991.

106. Kalla, R., Sinharoy, B., and TendlerJ.M. "IBM Power5 Chip: A Dual-Core Multithreaded Processors IEEE Micro Magazine, vol. 24, pp. 40-47, March-April 2004.

107. Kaposi, U.J., Rixner, S., Dally, W.J., Khailany, B., Ahn,J. H, Mattson, P., and Owens, J. D. "Programmable Stream Processors>>, IEEE Computer Magazine, vol. 36, pp. 54-62, Aug. 2003.

108. Kapil, S., M C Ghan, H., and LawrendraJ. "A Chip Multithreaded Processor for Network-Facing Workloads", IEEE Micro Magazine, vol. 24, pp. 20-30. March-April 2004.

109. Katz, R.H., and Borriello, G. Contemporary Logic Design, Upper Saddle River NJ: Prentice Hall, 2004.

110. Kaufman, C., Perlman, R., and Speciner, M. Network Security, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2002.

111. Kermarrec, A.-M., Kuz, I., Van Steen, M., and Tanenbaum, A. S. "A Framework for Consistent Replicated Web Objects", Proc. 18th Int'l. Conf. on Distr. Computing Syst, IEEE, pp. 276-284, 1998.

112. Kim, N. S., Austin, T., Blaauw, D., Mudge, T., Flautner, K, Hu,J. S., Irwin, M.J., Kandemir, M., and Narayanan, V. "Leakage Current: Moore's Law Meets Static Power", IEEE Computer Magazine, vol. 36, pp. 68-75, Dec. 2003.

113. Knuth, D. E. "An Empirical Study of FORTRAN Programs", Software -Practice & Experience, vol. 1, pp. 105-133, 1971.

114. Knuth, D. E. The Art of Computer Programming: Fundamental Algorithms, 3rd ed.. Reading, MA: Addison-Wesley, 1997.

115. Knuth, D. E. The Art of Computer Programming: Seminumerical Algorithms, 3rd ed, Reading, MA: Addison-Wesley, 1998.

116. Kogel, T., and Myer, H. "Heterogeneous MP-SoC: the solution to energy-efficient signal processing", Proc. 41st Ann. Conf. on Design Automation, IEEE, pp. 686-691,2004.

117. Kontothanassis, L., Hunt, G., Stets, R., Hardavellas, N, Cierniad, M., Parthasarathy, S., Meira, W., Dwarkadas, S., and Scott, M. VM-Based Shared Memory on Low Latency Remote Memory Access Networks, Proc. 24th Ann. Int'l. Symp. on Computer Arch, ACM, pp. 157-169, 1997.

118. Koren, I. Computer Arithmetic Algorithms, Natick, MA: A.K. Peters, 2002.

119. Koufaty, D., and Marr, D. T. "Hyperthreading Technology in the Netburst Microarchitecture", IEEE Micro Magazine, vol. 23, pp. 56-65, March-April 2003.

120. Kumar, R., Jouppi, N P., and Tullsen, D. M. "Conjoined-Core Chip Multi-processing", Proc. 37th Int'l Symp. on Microarchitecture, IEEE, pp. 195-206, 2004.

121. Lamport, L. "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", IEEE Trans, on Computers, vol. C-28, pp. 690-691, Sept. 1979.

122. LaRowe, R. P., and Ellis, C. S. "Experimental Comparison of Memory Management Policies for NUMA Multiprocessor, ACM Trans, on Computer Systems, vol. 9, pp. 319-363, Nov. 1991.

123. Lavagno, L. "Systems on a Chip: The Next Electronic Frontier", IEEE Micro Magazine, vol. 22, pp. 14-15, Sept.-Oct. 2002.

124. Lawton, G. "Will Network Processor Units Live up to Their Promise?", IEEE Computer Magazine, vol. 37, pp. 13-15, April 2004.

125. Lekkas, P. C. Network Processors: Architectures, Protocols, and Platforms, New York: McGraw-Hill, 2003.

126. Levine,]. R. Linkers and Loaders, San Francisco: Morgan Kaufmann, 2000.

127. Li, K, andHudak, P. "Memory Coherence in Shared Virtual Memory Systems", ACM Trans, on Computer Systems, vol. 7, pp. 321-359, Nov. 1989.

128. Lima, F., Carro, I, Velazco, R., and Reis, R. "Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller", Proc. Eighth IEEE Int'l On-Line Testing Workshop IEEE, p. 194, July 2002.

129. Lines, A. "Asynchronous Interconnect for Synchronous SoC Design", IEEE Micro Magazine, vol. 24, pp. 32-41, Jan.-Feb. 2004.

130. Lu, H., Cox, A. I, Dwarkadas, S., Rajamony, R., and Zwaenepoel, W. "Software Distributed Shared Memory Support for Irregular Applications", Proc. 6th Conf. on Prin. and Practice of Parallel Progr, pp. 48-56, June 1997.

131. Lukasiewicz, J. Aristotle's Syllogistic, 2nd ed, Oxford: Oxford University Press, 1958.

132. Lutz,]., and Hasan, A. "High Performance FPGA based Elliptic Curve Cryptographic Co-Processor", Proc. Int'l Conf. on Inf. Tech.: Coding and Computing, IEEE, pp. 486-492, 2004.

133. Lyytinen, K, and Yoo, Y. "Issues and Challenges in Ubiquitous Computing", Commun. of the ACM, vol. 45, pp. 63-65, Dec. 2002.

134. MacKenzie, LS., Phan, R. The 8051 Microcontroller, 4th ed. Upper Saddle River, NJ: Prentice Hall, 2005.

135. Mono, M. M, and Kirne, C. R. Logic and Computer Design Fundamentals, 3rd ed. Upper Saddle River, NJ: Prentice Hall, 2003.

136. Ma?1in, AJ., Nystrom, M., Papadantonakis, K, Penzes, P.I., Prakash, P., Wong, C.G., Chang,J., Ko, KS., Lee, B., Ou, F., PughJ, Talvala, E-V., TongJ.T., and Turn, A. "The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller", Proc. Ninth Int'l Symp. on Asynchronous Circuits and Systems IEEE, pp. 14-23, 2003.

137. Martin, R. P., Vahdat, A. M., Culler, D. E., and Anderson, T. E. "Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture", Proc. 24th Ann. Int'l. Symp. on Computer Arch, ACM, pp. 85-97, 1997.

138. Mayhew, D., and Krishnan, V. "PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects", Proc. 11th Symp. on High Perf. Interconnects IEEE, pp. 21-29, Aug. 2003.

139. Mazidi, M. A., McKinlay, and Mazidi, J. G. 8051 Microcontroller and Embedded Systems Upper Saddle River, NJ: Prentice Hall, 2005.

140. Mazidi, M. A., and Mazidi, J. G. The 80x86 IBM PC and Compatible Computers, 4th ed. Upper Saddle River, NJ: Prentice Hall, 2002.

141. McKnight, L.W., Howison,]., and Bradner, S. "Wireless Grids", IEEE Internet Computing, vol. 8, pp. 24-31, July-Aug. 2004.

142. McKusick, M. K, Bostic, K., Karels, M., and Quarterman, J. S. "The Design and Implementation of the 4.4 BSD Operating System", Reading, MA: Addison-Wesley, 1996.

143. McKusick, M. K.,Joy, W. N., Leffler, S.J., and Fabry, R. S. "A Fast File System for UNIX", ACM Trans, on Computer Systems, vol. 2, pp. 181-197, Aug. 1984.

144. McNairy, C, and Soltis, D. "Itanium 2 Processor Microarchitecture*, IEEE Micro Magazine, vol. 23, pp. 44-55, March-April 2003.

145. Min, R.,Jone, W.-Ben., and Hu, Y. "Location Cache: A Low-Power L2 Cache System*, Proce. 2004 Int'l Symp. on Low Power Electronics and Design, IEEE, pp. 120-125, Aug. 2004.

146. Messmer, H.-P. The Indispensible PC Hardware Book, 4th ed.. Reading, MA: Addison-Wesley, 2001.

147. Moudgill, M., and Vassiliadis, S. "Precise Interrupts*, IEEE Micro Magazine, vol. 16, pp. 58-67, Feb. 1996.

148. Mullender, S.J., and Tanenbaum, A. S. "Immediate Files*, Software - Practice and Experience, vol. 14, pp. 365-368, 1984.

149. Nesbit, K.J., and Smith, J. E. "Data Cache Prefetching Using a Global History Buffer*, Proc. 10th Int'l Symp. on High Perf. Computer Arch., IEEE, pp. 96-106, 2004.

150. Ng, S. W. "Advances in Disk Technology: Performance Issues*, IEEE Computer Magazine, vol. 31, pp. 75-81, May 1998.

151. NickollsJ., Madar, L.J. Ill Johnson, S., Rustagi, V., Unger, K., and Choudhury, M. "Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform*, IEEE Micro Magazine, vol. 23, pp. 29-43, March 2003.

152. Norton, P., and Goodman, J. Inside the PC, 8th ed., Indianapolis, IN: Sams, 1999.

153. Null, L., and Lobur,J. The Essentials of Computer Organization and Architecture, Sudbury, MA: Jones and Bartlett, 2003.

154. O'Connor, J.M., and Tremblay, M. "PicoJava-I: The Java Virtual Machine in Hardware*, IEEE Micro Magazine, vol. 17, pp. 45-53, March/April 1997.

155. Organick, E. The MULTICS System, Cambridge, MA: M.I.T. Press, 1972.

156. Oskin, M., Chong, F. T, and Chuang, I. L. "A Practical Architecture for Reliable Quantum Computers*, IEEE Computer Magazine, vol. 35, pp. 79-87, Jan. 2002.

157. Ouadjaout, S., andHouzet, D. "Easy SoC Design with VCI SystemC Adapters*, Proc. Digital System Design, IEEE, pp. 316-323, 2004.

158. Papaefstathiou, I., Nikolaou, NyA, Doshi, B., and Grosse, E. "Network Processors for Future High-End Systems and Applications*, IEEE Micro Magazine, vol. 24, pp. 7-9, Sept.-Oct. 2004.

159. Papamarcos, M., and Patel, J. "A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories*, Proc. 11th Ann. Int'l. Symp. on Computer Arch., ACM, pp. 348-354, 1984.

160. Parikh, D., Skadron, K., Zhang, Y., and Stan, M. "Power-Aware Branch Prediction: Characterization and Design*, IEEE Trans, on Computers, vol. 53, pp. 168-186, Feb. 2004.

161. Patterson, D. A. "Reduced Instruction Set Computers*, Commun. of the ACM, vol. 28, pp. 8-21, Jan. 1985.

162. Patterson, D. A., Gibson, G., and Katz, R. "A case for redundant arrays of inexpensive disks (RAID)", Proc. ACM SIGMOD Int'l. Conf. on Management of Data, ACM, pp. 109-166, 1988.

163. Patterson, D. A., and Hennessy, J. L. Computer Organization and Design, 3rd ed, San Francisco, CA: Morgan Kaufmann, 2005.

164. Patterson, D. A., and Sequin, C. H. "A VLSI RISC", IEEE Computer Magazine, vol. 15, pp. 8-22, Sept. 1982.

165. Paul, R. P. SPARC Architecture, Assembly Language, Programming, and C, Engle-wood Cliffs, NJ: Prentice Hall, 1994.

166. Pfister, G. F. In Search of Clusters, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 1998.

167. Popescu, B.C., Steen, M. Van, and Tanenbaum, A.S. "A Security Architecture for Object-Based Distributed Systems", Proc. 18th Annual Computer Security Appl. Conf, ACM, pp. 161-171, 2002.

168. Fountain, D. "Pentium: More RISC than CISC", Byte, vol. 18, pp. 195-204, Sept. 1993.

169. Price, D. "A History of Calculating Machines", IEEE Micro Magazine, vol. 4, pp. 22-52, Feb.1984.

170. Radin, G. "The 801 Minicomputers Computer Arch. News, vol. 10, pp. 39-47, March 1982.

171. Raman, S. K., Pentkovski, V., and Keshava, J. implementing Streaming SIMD Extensions on the Pentium III Processors IEEE Micro Magazine, vol. 20, pp. 47-57, July-Aug. 2000.

172. Ravikumar, CP. "Multiprocessor Architectures for Embedded System-on-a-Chip Applications Proc. 17th Int'l Conf. on VLSI Design, IEEE, pp. 512-519, Jan. 2004.

173. Ritchie, D. M, and Thompson, K. "The UNIX Time-Sharing Systems Commun. of the ACM, vol. 17, pp. 365-375, July 1974.

174. Robinson, G.S. "Toward the Age of Smarter Storages IEEE Computer Magazine, vol. 35, pp. 35-41, Dec. 2002.

175. Rosenblum, M., and OusterhoutJ. K. "The Design and Implementation of a Log-Structured File Systems Proc. Thirteenth Symp. on Operating System Principles, ACM, pp. 1-15, 1991.

176. Roth, C. H. Fundamentals of Logic Design, 5th ed, Florence, KY: Thomson Engineering, 2003.

177. Russinovich, M. E., and Solomon, D. A. Microsoft Windows Internals, 4th ed, Redmond, WA: Microsoft Press, 2005.

178. Rusu, S., Muljono, H, and Cherkauer, B. "Itanium 2 Processor 6M", IEEE Micro Magazine, vol. 24, pp. 10-18, March-April 2004.

179. Saha, D., and Mukherjee, A. "Pervasive Computing: A Paradigm for the 21st Centurys IEEE Computer Magazine, vol. 36, pp. 25-31, March 2003.

180. Sakamura, K. "Making Computers Invisibles IEEE Micro Magazine, vol. 22, pp. 7-11,2002.

181. Salomon, D. Assemblers and Loaders, Englewood Cliffs, NJ: Prentice Hall, 1993.

182. Scales, D.J., Gharachorloo, K, and Thekkath, CA. "Shasta: A Low-Overhead Software-Only Approach for Supporting Fine-Grain Shared Memory", Proc. 7th Int'l. Conf. on Arch. Support for Prog. Long, and Oper. Syst, ACM, pp. 174-185, 1996.

183. Scheible,]. P. "A Survey of Storage Options", IEEE Computer Magazine, vol. 35, pp. 42-46, Dec. 2002.

184. Seltzer, M, Bostic, K, McKusick, M. K, and Staelin, C. "An Implementation of a Log-Structured File System for UNIX", Proc. Winter 1993 USENIX Technical Conf, pp. 307-326, 1993.

185. Shanley, T., and Anderson, D. PCI System Architecture, 4th ed.. Reading, MA: Addison-Wesley, 1999.

186. Shiver, B., and Smith, B. The Anatomy of a High-Performance Microprocessor: A Systems Perspective, Los Alamitos, CA: IEEE Computer Society, 1998.

187. Sima, D. "Superscalar Instruction Issue", IEEE Micro Magazine, vol. 17, pp. 28-39, Sept./Oct 1997.

188. Sima, D., Fountain, T., and Kacsuk, P. Advanced Computer Architectures: A Design Space Approach, Reading, MA: Addison-Wesley, 1997.

189. Slater, R. Portraits in Silicon, Cambridge, MA: M.I.T. Press, 1987.

190. Snir, M, Otto, S,W., Huss-Lederman, S., Walker, D.W., and Dongarra,]. MPI: The Complete Reference Manual, Cambridge, MA: M.I.T. Press, 1996.

191. Sohi, G. S., and Roth, A. "Speculative Multithreaded Processors", IEEE Computer Magazine, vol. 34, pp. 66-73, April 2001.

192. Solari, E., and Congdon, B. PCI Express Design & System Architecture, Research Tech, Inc., 2005.

193. Solari, E., and Willse, G. PCI and PCI-X Hardware and Software, 6th ed, San Diego, CA: Annabooks, 2004.

194. Stallings, W. Computer Organization and Architecture, 6th ed. Upper Saddle River, NJ: Prentice Hall, 2003.

195. Stenstrom, P., Hagersten, E., Lilja, D.J., Martonosi, M, and Venugopal, M. "Trends in Shared Memory Multiprocessing^ IEEE Computer Magazine, vol. 30, pp. 44-50, Dec. 1997.

196. Stets, R., Dwarkadas, S., Hardavellas, N., Hunt, G., Kontothanassis, I, Partha-sarathy, S., and Scott, M. "CASHMERE-2L: Software Coherent Shared Memory on Clustered Remote-Write Networks", Proc. 16th Symp. on Operating Systems Principles, ACM, pp. 170-183, 1997.

197. Suh, T, Lee, H-H S., Blough, D. M. integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1", IEEE Micro Magazine, vol. 24, pp. 33-41, July 2004.

198. Summers, C. K. ADSL: Standards, Implementation, and Architecture, Boca Raton, FL: CRC Press, 1999.

199. Sunderram, V. B. "PVM: A Framework for Parallel Distributed Computing*, Concurrency: Practice and Experience, vol. 2, pp. 315-339, Dec. 1990.

200. Swan, R. J., Fuller, S. H., and Siewiorek, D. P. "Cm* -A Modular Multiprocessor*, Proc. NCC, pp. 645-655, 1977.

201. Tan, W. M. Developing USB PC Peripherals, San Diego, CA: Annabooks, 1997.

202. Tanenbaum, A. 5. "Computer Networks*, Upper Saddle River, NJ: Prentice Hall, 2003.

203. Tanenbaum, A. S. implications of Structured Programming for Machine Architecture*, Commun. of the ACM, vol. 21, pp. 237-246, Mar. 1978.

204. Tanenbaum, A. S. Operating Systems: Design and Implementation. Upper Saddle River, NJ: Prentice Hall, 1987.

205. Tanenbaum, A. 5., and Woodhull, A. W. Operating Systems: Design and Implementation. Upper Saddle River, NJ: Prentice Hall, 1997.

206. Thompson, K. "UNIX Implementation*, Bell Syst. Tech. J., vol. 57, pp. 1931-1946, July-Aug. 1978.

207. Treleaven, P. "Control-Driven, Data-Driven, and Demand-Driven Computer Architecture*, Parallel Computing, vol. 2, 1985.

208. Tremblay, M. and 0'connor,J. M. "UltraSPARC I: A Four-Issue Processor Supporting Multimedia*, IEEE Micro Magazine, vol. 16, pp. 42-50, April 1996.

209. Triebel, W. A. The 80386, 80486, and Pentium Processor, Upper Saddle River, NJ: Prentice Hall, 1998.

210. Tuck, N., and Tullsen, D. M. "Initial Observations of the Simultaneous Multithreading Pentium 4 Processor*, Proc. 12th Int'l Conf. on Parallel Arch, and Compilation Techniques, IEEE, pp. 26-35, 2003.

211. Unger, 5. H. "A Computer Oriented Toward Spatial Problems*, Proc. IRE, vol. 46, pp. 1744-1750, 1958.

212. Vahalia, U. UNIX Internals, Upper Saddle River, NJ: Prentice Hall, 1996.

213. Vahid, F. "The Softening of Hardware*, IEEE Computer Magazine, vol. 36, pp. 27-34, April 2003.

214. Van Steen, M., Homburg, P. C, and Tanenbaum, A. S. "The Architectural Design of Globe: A Wide-Area Distributed System*, IEEE Concurrency, vol. 7, pp. 70-78, Jan.-March 1999.

215. Vetter, P., Goderis, D., Verpooten, L., and Granger, A. "Systems Aspects of APON/ VDSL Deployment*, IEEE Commun. Magazine, vol. 38, pp. 66-72, May 2000.

216. Weaver, D. L., and Germond, T. The SPARC Architecture Manual, Version 9, Englewood Cliffs, NJ: Prentice Hall, 1994.

217. Weiser, M. "The Computer for the 21st Century*, IEEE Pervasive Computing, vol 1, pp. 19-25, Jan.-March 2002; originally published in Scientific American, Sept. 1991.

218. Wilkes, M. V. "Computers Then and Now*, J. ACM, vol. 15, pp. 1-7, Jan. 1968.

219. Wilkes, M. V. "The Best Way to Design an Automatic Calculating Machines Proc. Manchester Univ. Computer Inaugural Conf, 1951.

220. Wilson, J. "Challenges and Trends in Processor Designs IEEE Computer Magazine, vol. 31, pp. 39-48, Jan. 1998.

221. Wilson, P. "Floating-Point Survival Kits Byte, vol. 13, pp. 217-226, March 1988.

222. Wolf, W. "The Future of Multiprocessor Systems-on-Chips", Proc. 41st Ann. Conf. on Design Automation, IEEE, pp. 681-685, 2004.

Программирование на языке ассемблера || Оглавление || Приложение А. Двоичные числа